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dc.contributor.authorLee, CLen_US
dc.contributor.authorChern, HNen_US
dc.contributor.authorLiao, MSen_US
dc.contributor.authorWang, HMen_US
dc.date.accessioned2014-12-08T15:27:45Z-
dc.date.available2014-12-08T15:27:45Z-
dc.date.issued1995en_US
dc.identifier.isbn0-7803-2764-0en_US
dc.identifier.issn0195-623Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/20013-
dc.language.isoen_USen_US
dc.subjectmulti-valued logicen_US
dc.subjectdouble-gate thin film transistoren_US
dc.subjectSRAMen_US
dc.subjectcircuit designen_US
dc.titleOn designing of 4-valued memory with double-gate TFTen_US
dc.typeProceedings Paperen_US
dc.identifier.journal1995 25TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGSen_US
dc.citation.spage187en_US
dc.citation.epage192en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1995BE33A00029-
Appears in Collections:Conferences Paper