標題: MECHANISMS OF INTERFACE TRAP-INDUCED DRAIN LEAKAGE CURRENT IN OFF-STATE N-MOSFETS
作者: CHANG, TE
HUANG, CM
WANG, TH
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-四月-1995
摘要: An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFET's after hot carrier stress. In the model a complete band-trap-band leakage path is formed at the Si/SiO2 interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 mu m n-MOSFET was subjected to a de voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsible for the leakage current at a large drain-to-gate bias (V-dg) The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression Delta I-d = A exp (B-it/F). The value of Bit about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V-dg decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V-dg, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant.
URI: http://dx.doi.org/10.1109/16.372079
http://hdl.handle.net/11536/1989
ISSN: 0018-9383
DOI: 10.1109/16.372079
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 42
Issue: 4
起始頁: 738
結束頁: 743
顯示於類別:期刊論文


文件中的檔案:

  1. A1995QP59000024.pdf