標題: A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs
作者: Yeh, Kuo-Liang
Guo, Jyh-Chyurn
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Effective mobility;effective width;fringing capacitance;open deembedding;parasitic capacitances
公開日期: 1-九月-2011
摘要: The impact of layout-dependent parasitic capacitances on extraction of inversion carrier density Q(inv) and effective mobility mu(eff) has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the extrinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such as gate finger sidewall and finger-end fringing capacitances, i.e., C(of) and C(f(poly-end)), respectively. Both categories of parasitic capacitance lead to overestimated Q(inv) and underestimated mu(eff). The increase in effective channel width W(eff) due to Delta W from shallow trench isolation (STI) top-corner rounding may compensate mu(eff) degradation due to STI stress. The tradeoff between mu(eff) and W(eff) determines the impact of width scaling on I(DS) and G(m). A new method based on the measured S-parameters, open-M1 deembedding, and Raphael simulation can precisely determine the mentioned parameters associated with the intrinsic channel and realize accurate extraction of mu(eff) in multifinger MOSFETs with various layouts and narrow widths down to 0.125 mu m.
URI: http://dx.doi.org/10.1109/TED.2011.2158105
http://hdl.handle.net/11536/19814
ISSN: 0018-9383
DOI: 10.1109/TED.2011.2158105
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 58
Issue: 9
起始頁: 2838
結束頁: 2846
顯示於類別:期刊論文


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  1. 000294175900004.pdf