標題: VLSI Architecture for Real-Time HD1080p View Synthesis Engine
作者: Horng, Ying-Rung
Tseng, Yu-Cheng
Chang, Tian-Sheuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: 3-D video coding;view synthesis;VLSI design
公開日期: 1-九月-2011
摘要: This paper presents a real-time HD1080p view synthesis engine based on the reference algorithm from 3-D video coding team by solving high computational complexity and high memory cost problems. For the computational complexity, we propose the bilinear interpolation to simplify the hole filling process, and the Z scaling method with floating-point format to reduce the cost of homography calculation. For the memory cost, we propose the frame-level pipelining to reduce the requirement of warped depth maps, and the column-order warping method to remove the Z-buffer in occlusion handling. With the 90nm complementary metal-oxide-semiconductor technology, our view synthesis engine can archive the throughput of 32.4 f/s for HD1080p videos with the gate count of 268.5K and the internal memory of 69.4 kbytes. The experimental result shows our implementation has the similar synthesis quality as the original reference algorithm.
URI: http://dx.doi.org/10.1109/TCSVT.2011.2148410
http://hdl.handle.net/11536/19681
ISSN: 1051-8215
DOI: 10.1109/TCSVT.2011.2148410
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
Volume: 21
Issue: 9
起始頁: 1329
結束頁: 1340
顯示於類別:期刊論文


文件中的檔案:

  1. 000294669900013.pdf