標題: EFFECTS OF POLYSILICON ELECTRON-CYCLOTRON-RESONANCE ETCHING ON ELECTRICAL CHARACTERISTICS OF GATE OXIDES
作者: KANG, TK
UENG, SY
DAI, BT
CHEN, LP
CHENG, HC
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: ECR ETCHING;RADIATION DAMAGE;SIO2/SI INTERFACE TRAP STATE;POSITIVE CHARGE
公開日期: 1-五月-1995
摘要: In spite of the small amount of damage induced by Electron Cyclotron Resonance (ECR) etching, the radiation damage due to vacuum ultraviolet (VUV) photons from the high-density plasma still causes several problems. The leakage currents of the metal-oxide-semiconductor (MOS) capacitors with ECR-etched polysilicon gates are found to be higher than those of the control with wet etching. The leakage mechanism is therefore investigated in detail. The ions and radicals of the ECR plasma can directly attack the peripheral gate oxide and form the surface-damaged layer. In addition, the VUV photons will deeply impact the oxide interior and induce positive charges and interface trap states. ii dilute HF solution can effectively remove the surface damage layer. Annealing at 400 degrees C for 30 min can eliminate completely the positive charges. Furthermore, the SiO2/Si interface trap states are completely removed as the annealing time is raised to 60 min.
URI: http://dx.doi.org/10.1143/JJAP.34.2272
http://hdl.handle.net/11536/1965
ISSN: 0021-4922
DOI: 10.1143/JJAP.34.2272
期刊: JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS
Volume: 34
Issue: 5A
起始頁: 2272
結束頁: 2277
顯示於類別:期刊論文


文件中的檔案:

  1. A1995RF66200013.pdf