標題: Novel strategies of FSG-CMP for within-wafer uniformity improvement and wafer edge yield enhancement beyond 0.18 micro technologies
作者: Chen, KW
Wang, YL
Chang, L
Liu, CW
Lin, YK
Wang, TC
Chang, ST
Lo, KY
材料科學與工程學系
Department of Materials Science and Engineering
關鍵字: fluorinated silicate glass (FSG);chemical-mechanical planarization (CMP);uniformity;wafer edge;polishing path;head sweep profile;and edge sprayer
公開日期: 2001
摘要: The low-K films and higher multiple stacked layers would be widely applied for ultra large-scale integrated circuits [1][2]. However for 8" (200mm) or 12" (300mm) wafer the phenomena of wafer edge collapsing in higher interlayer low-K dielectric film causes from CMP polishing effect. (Shown in Fig. 1). Conventionally a amount of work has been developed in the optimization of different parameters, such as low pressure and high speed [3], metal dummy filling [4], harder pad used [4], and design of polishing head in order to resolve the problems. But these methods only engaged in design of experiment, not addressed in CMP theory of edge collapsing and controlling way. In this paper we will discuss the theory applied in Preston equation to explain the polishing behavior in wafer edge. In advance, to implement the theory, we adopted novel strategies, including of different polishing head (sweep) vibration and pad edge sprayer methods, even new wafer retaining ring design and novel delivery slurry methods in advance. The characteristics of within wafer nonuniformity and edge profile against CMP polishing low-k films, fluorinated silicate glass (FSG), would be evaluated in this new strategy action. Besides, the dimension of metal line and VIA, and edge die-yield can be directly responded to the edge profile improvement. From the action results, the average 7 similar to 10% yield improvement of 0.18 technology can be achieved, especially 15% edge-die yield improvement. The edge profile could promote the phenomena of no collapsing from the original 75 mm to 95 mm of wafer center-to-edge distance, excluding 3 mm edge of 8-inch wafer. These high efficient strategies for within-wafer planarization and edge profile is also proven and fulfilled with the reducing over 50% VIA CD deviation on the rule of lithography.
URI: http://hdl.handle.net/11536/19050
http://dx.doi.org/10.1109/ISSM.2001.962962
ISBN: 0-7803-6731-6
DOI: 10.1109/ISSM.2001.962962
期刊: 2001 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS
起始頁: 259
結束頁: 261
顯示於類別:會議論文


文件中的檔案:

  1. 000172618300062.pdf