標題: A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxide
作者: Chung, SS
Chen, SJ
Yang, CK
Cheng, SM
Lin, SH
Sheng, YC
Lin, HS
Hung, KT
Wu, DY
Yew, TR
Chien, SC
Liou, FT
Wen, F
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2002
摘要: For the first time, an improved charge pumping (CP) method has been implemented for direct determination of the interface traps in ultra-short gate length CMOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12-16A gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has, been demonstrated successfully for various RTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. Moreover, it can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relating to the interface trap generation.
URI: http://hdl.handle.net/11536/18838
http://dx.doi.org/10.1109/VLSIT.2002.1015394
ISBN: 0-7803-7312-X
DOI: 10.1109/VLSIT.2002.1015394
期刊: 2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS
起始頁: 74
結束頁: 75
Appears in Collections:Conferences Paper


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