標題: DISTRIBUTED FAULT SIMULATION FOR SEQUENTIAL-CIRCUITS BY PATTERN PARTITIONING
作者: WU, WC
LEE, CL
CHEN, JE
LIN, WY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: DISTRIBUTED MACHINES;MULTIPROCESSORS;PATTERN PARTITIONING
公開日期: 1-Jul-1995
摘要: The paper investigates distributed fault simulation by pattern partitioning for sequential circuits. Simulation is done by making each distributed machine perform fault-free simulation with preceding patterns and then perform fault simulation with its own patterns. The fault simulation is accelerated since the number of patterns needed to be performed fault simulation for each machine is reduced by a factor of n, the number of machines, and the faults detected by any machine are dropped through communication of the network. A superlinear speedup can be obtained because this method can automatically remove the Case 1 faults, which are time consuming faults and would be considered to be undetected in the traditional three-valued fault simulation but are in fact truly detected. A mathematical model is also presented to predict the performance of the distributed fault simulation.
URI: http://dx.doi.org/10.1049/ip-cdt:19951867
http://hdl.handle.net/11536/1834
ISSN: 1350-2387
DOI: 10.1049/ip-cdt:19951867
期刊: IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES
Volume: 142
Issue: 4
起始頁: 287
結束頁: 292
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  1. A1995RR36400007.pdf