標題: COMPLEMENTARY-SCR ESD PROTECTION CIRCUIT WITH INTERDIGITATED FINGER-TYPE LAYOUT FOR INPUT PADS OF SUBMICRON CMOS ICS
作者: KER, MD
WU, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-七月-1995
摘要: A new ESD protection circuit with complementary SCR structures and junction diodes is proposed, This complementary-SCR ESD protection circuit with interdigitated finger-type layout has been successfully fabricated and verified in a 0.6-mu m CMOS SRAM technology with LDD process, The proposed ESD protection circuit can be free of VDD-to-VSS latchup issue under 5-V VDD operation by means of base-emitter shorting method, To compensate the degradation on latching capability of lateral SCR devices in the ESD protection circuit caused by base-emitter shorting method, the p-well to p-well spacing of lateral BJT's in the lateral SCR devices is reduced to lower its ESD-trigger voltage and to enhance turn-on speed of positive-feedback regeneration in the lateral SCR devices. This ESD protection circuit can perform high ESD failure threshold in a small layout area, so it is very suitable for submicron CMOS VLSI/ULSI's in high-pin-count or high-density applications.
URI: http://dx.doi.org/10.1109/16.391212
http://hdl.handle.net/11536/1821
ISSN: 0018-9383
DOI: 10.1109/16.391212
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 42
Issue: 7
起始頁: 1297
結束頁: 1304
顯示於類別:期刊論文


文件中的檔案:

  1. A1995RE53000014.pdf