Full metadata record
DC FieldValueLanguage
dc.contributor.authorYu, DSen_US
dc.contributor.authorChin, Aen_US
dc.contributor.authorLaio, CCen_US
dc.contributor.authorLee, CFen_US
dc.contributor.authorCheng, CFen_US
dc.contributor.authorChen, WJen_US
dc.contributor.authorZhu, Cen_US
dc.contributor.authorLi, MFen_US
dc.contributor.authorYoo, WJen_US
dc.contributor.authorMcAlister, SPen_US
dc.contributor.authorKwong, DLen_US
dc.date.accessioned2014-12-08T15:25:43Z-
dc.date.available2014-12-08T15:25:43Z-
dc.date.issued2004en_US
dc.identifier.isbn0-7803-8684-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/18124-
dc.identifier.urihttp://dx.doi.org/10.1109/IEDM.2004.1419101en_US
dc.description.abstractFor the first time, we demonstrate 3D integration of self-aligned IrO2(Hf)/LaAlO3/GOI CMOSFETs above 0.18 pm Si CMOSFETs. At EOT=1.4nm, the novel IrO2(Hf) dual gates (4.4 and 5.1 eV workfunction) on control 2D LaAlO3/Si devices have high electron and hole mobilities of 203 and 67 cm(2)/Vs. On the 3D structure the LaAlO3/GOI shows even higher 389 and 234 cm(2)/Vs mobilities, and process compatibility with current Si VLSI. The higher drive current, larger integration density, shorter interconnects distance, and simple process of 3D approach can help solve the AC power issue and 2D scaling limitation.en_US
dc.language.isoen_USen_US
dc.title3D GOI CMOSFETs with novel IrO2(Hf) dual gates and high-kappa dielectric on 1P6M-0.18 mu m-CMOSen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/IEDM.2004.1419101en_US
dc.identifier.journalIEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGESTen_US
dc.citation.spage181en_US
dc.citation.epage184en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000227158500040-
Appears in Collections:Conferences Paper


Files in This Item:

  1. 000227158500040.pdf