標題: Universal architectures for Reed-Solomon error-and-erasure decoder
作者: Chang, Fu-Ke
Lin, Chien-Ching
Chang, Hsie-Chia
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2005
摘要: This paper presents the universal architecture for Reed Solomon (RS) error-and-erasure decoder that can accommodate any codeword with different code parameters and finite field definitions. In comparison with other reconfigurable RS decoders, the proposed design, based on the Montgomery multiplication algorithm, can support various finite field degrees, different primitive polynomials, and erasure decoding functions. In addition, the decoder features an on-the-fly finite field inversion table for high speed error evaluation. The area efficient design approach is also presented Implemented with 1.2V 0.13 mu m 1P8M technology, this decoder, correcting up to 16 errors, can operate at 300MHz and reach a 2.4Gb/s data rate. The total gate count is about 54K and the core size is 0.36mm(2). The average power consumption is 20.2m W.
URI: http://hdl.handle.net/11536/17993
http://dx.doi.org/10.1109/ASSCC.2005.251707
ISBN: 0-7803-9162-4
DOI: 10.1109/ASSCC.2005.251707
期刊: 2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS
起始頁: 229
結束頁: 232
Appears in Collections:Conferences Paper


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