Title: SUPPRESSION OF BORON PENETRATION IN BF2-IMPLANTED P-TYPE GATE MOSFET BY TRAPPING OF FLUORINES IN AMORPHOUS GATE
Authors: LIN, CY
CHANG, CY
HSU, CCH
電控工程研究所
奈米中心
Institute of Electrical and Control Engineering
Nano Facility Center
Issue Date: 1-Aug-1995
Abstract: This work reports the use of amorphous/polysilicon gate electrode in BF2-implanted poly-gated P-MOSFET's to suppress the boron penetration, SIMS analysis clearly illustrates that fluorine prefers to accumulate in the layer of amorphous silicon. The retardation of boron diffusion is therefore achieved by the trapping of fluorine in the amorphous layer of stacked amorphous/polysilicon (SAP) p-type gate due to a lower diffusion rate of fluorine in the amorphous silicon layer. Polysilicon depletion effect did not become more severe by introducing the amorphous silicon. In addition, gate oxide reliability is not degraded by using this gate structure. Results show that the structure is a promising gate electrode for future dual-poly gate CMOS technology development.
URI: http://dx.doi.org/10.1109/16.398666
http://hdl.handle.net/11536/1792
ISSN: 0018-9383
DOI: 10.1109/16.398666
Journal: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 42
Issue: 8
Begin Page: 1503
End Page: 1509
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  1. A1995RJ15000015.pdf