標題: Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process
作者: Hsu, Sheng-Fu
Ker, Ming-Dou
Lin, Geeng-Lih
Jou, Yeh-Ning
電機學院
College of Electrical and Computer Engineering
公開日期: 2006
摘要: The dependence of device structures and layout parameters on latchup immunity in high-voltage (HV) 40-V CMOS process have been verified with silicon test chips and investigated with device simulation. It was demonstrated that a specific test structure considering the parasitic silicon controlled rectifier (SCR) resulting from isolated asymmetric HV NMOS and HV PMOS has the best latchup immunity. The test structures and simulation methodology proposed in this work can be applied to extract safe and compact design rule for latchup prevention in HV CMOS process. All the test chips are fabricated in a 0.25-mu m 40-V CMOS technology.
URI: http://hdl.handle.net/11536/17477
http://dx.doi.org/10.1109/RELPHY.2006.251206
ISBN: 0-7803-9498-4
DOI: 10.1109/RELPHY.2006.251206
期刊: 2006 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 44TH ANNUAL
起始頁: 140
結束頁: 144
Appears in Collections:Conferences Paper


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