標題: A low-voltage CMOS LNA design utilizing the technique of capacitive feedback matching network
作者: Wu, Chung-Yu
Shahroury, Fadi Riad
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2006
摘要: In this paper, a CMOS low noise amplifier (LNA) with a new input matching topology has been proposed, analyzed, and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0.18-mu m 1P6M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NFmin of 4.46 dB. The reverse isolation S12 of the LNA can achieve -40 dB and the input and output return losses are better than -11 dB. The input 1-dB compression point is -11 dBm. This LNA drains 10 mA from the supply voltage of 1 V.
URI: http://hdl.handle.net/11536/17418
http://dx.doi.org/10.1109/ICECS.2006.379705
ISBN: 978-1-4244-0394-3
DOI: 10.1109/ICECS.2006.379705
期刊: 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3
起始頁: 78
結束頁: 81
Appears in Collections:Conferences Paper


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