Title: Novel architecture for ATM QoS management
Authors: Tsai, JM
Lee, CY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: ATM systems;ISDN;quality of service;scheduling
Issue Date: 1-Dec-1997
Abstract: A novel architecture and an enhanced approach to a flexible, starvation-free ATM QoS managing function is proposed. To meet the stringent timing constraint of the delay QoSs, both high-speed sorter and subtracter are exploited to sort the priority value as well as to process the priority value. The subtractive policy is used to prevent starvation and to assign the priority of each output queue. In addition, to prevent underflow of priority value and to process the empty queue situation, both renormalisation circuit and empty flag are exploited to perform the normalisation function. Simulation results show that the throughput of the enhanced architecture is more than 50 M output requests per second (21.2 Gbit/s for ATM cells) by using a 1.2 mu m CMOS process. The proposed architecture can be cascadable, making it very suitable for complex QoS management.
URI: http://hdl.handle.net/11536/174
ISSN: 1350-2425
Journal: IEE PROCEEDINGS-COMMUNICATIONS
Volume: 144
Issue: 6
Begin Page: 412
End Page: 418
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