標題: MULTIPLE-INPUTS SYSTOLIC PRIORITY QUEUE FOR FAST SEQUENTIAL-DECODING OF CONVOLUTIONAL-CODES
作者: KUO, HC
WEI, CH
電控工程研究所
電信研究中心
Institute of Electrical and Control Engineering
Center for Telecommunications Research
關鍵字: CONVOLUTIONAL DECODING;METRIC SEARCHING;SEQUENTIAL DECODING;SYSTOLIC ARRAYS;TRELLIS MODULATION
公開日期: 1-十月-1995
摘要: The operating speed of a sequential decoder with stack algorithm is usually limited by the time to search the best node for further extension. This problem can be completely alleviated by using the systolic priority queue to replace the stack memory. However, the systolic priority queues developed previously are accessible only in the cases when the number of inputs processed is small. This is because the complexity of a queue grows up quickly as the volume of data flowing through it increases. Since the largest amount of data flowing through a systolic priority queue is equal to the number of inputs to this queue, the systolic priority queue is not suitable for a system with many inputs. A modified version of previously developed circuits is proposed. The number of transmission gates required in this circuit is proportional to 3N instead of N-2, where N is the number of inputs. And the total number of control signals is proportional to 3N(2) instead of N-3. But the number of comparators required is proportional to C-2(N+1), as before. This modified circuit can be used in cases where the number of inputs is small (N less than or equal to 8). A new algorithm for the multiple-inputs systolic priority queue (MISPQ) is proposed. By using this algorithm, a MISPQ may be implemented with several smaller queues, each is used to process a part of data in the MISPQ. Since the volume of data flowing through each queue is small, these queues will be simpler. However, some additional circuits should be used for the interactions between queues. A circuit for implementing this algorithm is presented and its complexity is analysed. The number of transmission gates for the MISPQ is proportional to 3N, the number of control signals is proportional to (3N(2)/2), and the number of comparators is proportional to 4C(2)(N/2+1). Thus this new architecture is feasible for large N (e.g. N greater than or equal to 8).
URI: http://dx.doi.org/10.1049/ip-cds:19952163
http://hdl.handle.net/11536/1712
ISSN: 1350-2409
DOI: 10.1049/ip-cds:19952163
期刊: IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS
Volume: 142
Issue: 5
起始頁: 282
結束頁: 292
顯示於類別:期刊論文


文件中的檔案:

  1. A1995TC09200003.pdf