標題: Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology
作者: Lin, Chun-Yu
Chu, Li-Wei
Tsai, Shiang-Yu
Ker, Ming-Dou
電子工程學系及電子研究所
光電工程學系
顯示科技研究所
Department of Electronics Engineering and Institute of Electronics
Department of Photonics
Institute of Display
關鍵字: CMOS;electrostatic discharge (ESD) protection;radio frequency (RF);V-band
公開日期: 1-九月-2012
摘要: Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, an on-chip ESD protection design must be included in the RF circuits. As the RF circuits operate in the higher frequency band, the parasitic effect from ESD protection circuit must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier with less RF performance degradation, two new ESD protection circuits were studied in a 65-nm CMOS process. Such compact ESD protection circuits have been successfully verified in silicon chip to achieve the 2-kV human-body-model ESD robustness with the low insertion loss in small layout area. With the better performances, the proposed ESD protection circuits were very suitable for V-band RF ESD protection.
URI: http://dx.doi.org/10.1109/TDMR.2012.2188405
http://hdl.handle.net/11536/16883
ISSN: 1530-4388
DOI: 10.1109/TDMR.2012.2188405
期刊: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
Volume: 12
Issue: 3
起始頁: 554
結束頁: 561
顯示於類別:期刊論文


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