標題: Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology
作者: Yeh, Chih-Ting
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: gate leakage;power-rail electrostatic discharge (ESD) clamp circuit;silicon-controlled rectifier (SCR)
公開日期: 1-Oct-2012
摘要: An ultralow-leakage power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide devices and with silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. By reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit, the proposed power-rail ESD clamp circuit can achieve an ultralow standby leakage current. In addition, the ESD-transient detection circuit can be totally embedded in the SCR device bymodifying the layout structure. From the measured results, the proposed power-rail ESD clamp circuit with an SCR width of 45 mu m can achieve 7-kV human-body-model and 350-V machine-model ESD levels under the ESD stress event while consuming only a standby leakage current in the order of nanoamperes at room temperature under the normal circuit operating condition with 1-V bias.
URI: http://dx.doi.org/10.1109/TED.2012.2209120
http://hdl.handle.net/11536/16813
ISSN: 0018-9383
DOI: 10.1109/TED.2012.2209120
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 59
Issue: 10
起始頁: 2626
結束頁: 2634
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