標題: A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications
作者: Yen, Shao-Wei
Hung, Shiang-Yu
Chen, Chih-Lung
Chang, Hsie-Chia
Jou, Shyh-Jye
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: IEEE 802.15.3c;low-density parity-check (LDPC) codes;row-based layered scheduling
公開日期: 1-九月-2012
摘要: "An LDPC codec chip supporting four code rates of IEEE 802.15.3c applications is presented. After utilizing row-based layered scheduling, the normalized min-sum (NMS) algorithm can reduce half of the iteration number while maintaining similar performance. According to the unique code structure of the parity-check matrix, a reconfigurable 8/16/32-input sorter is designed to deal with LDPC codes in four different code rates. Both sorter input reallocation and pre-coded routing switch are proposed to alleviate routing complexity, leading to 64% input reduction of multiplexers. In addition, an adder-accumulator-shift register (AASR) circuit is proposed for the LDPC encoder to reduce hardware complexity. After implemented in 65-nm 1P10M CMOS process, the proposed LDPC decoder chip can achieve maximum 5.79-Gb/s throughput with the hardware efficiency of 3.7 Gb/s mm(2) and energy efficiency of 62.4 pJ/b, respectively."
URI: http://hdl.handle.net/11536/16712
ISSN: 0018-9200
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 47
Issue: 9
結束頁: 2246
顯示於類別:期刊論文


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  1. 000308007900025.pdf