Title: Testing Methodology of Embedded DRAMs
Authors: Yang, Hao-Yu
Chang, Chi-Min
Chao, Mango C. -T.
Huang, Rei-Fu
Lin, Shih-Chin
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
Keywords: Embedded-DRAM (eDRAM);fault model;retention;error-correction-code
Issue Date: 1-Sep-2012
Abstract: "The embedded-DRAM(eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core."
URI: http://hdl.handle.net/11536/16588
ISSN: 1063-8210
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 20
Issue: 9
End Page: 1715
Appears in Collections:Articles


Files in This Item:

  1. 000306518900015.pdf