|標題:||Testing Methodology of Embedded DRAMs|
Chao, Mango C. -T.
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
|關鍵字:||Embedded-DRAM (eDRAM);fault model;retention;error-correction-code|
|摘要:||"The embedded-DRAM(eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core."|
|期刊:||IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS|