Title: A shift register architecture for high-speed data sorting
Authors: Lee, CY
Tsai, JM
Department of Electronics Engineering and Institute of Electronics
Issue Date: 1-Dec-1995
Abstract: This paper presents a shift-register architecture or SRA, for data sorting applications. The operations performed by the proposed architecture are (1) shift right, (2) shift left, (3) load, and (4) initialize. Sorting operations, such as insert and delete, can be realized by the combination of these 4 basic operations. The architecture is very regular and mainly composed of two basic cells, sort-cell and compare-cell. The latter is designed to generate control signals orchestrating the operation of sort cells which contain the sorted input sequences. Experimental results show that a single chip solution can achieve real-time performance based on 1.2 mu m CMOS double-metal technology.
URI: http://dx.doi.org/10.1007/BF02107058
ISSN: 0922-5773
DOI: 10.1007/BF02107058
Volume: 11
Issue: 3
Begin Page: 273
End Page: 280
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