標題: A shift register architecture for high-speed data sorting
作者: Lee, CY
Tsai, JM
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-十二月-1995
摘要: This paper presents a shift-register architecture or SRA, for data sorting applications. The operations performed by the proposed architecture are (1) shift right, (2) shift left, (3) load, and (4) initialize. Sorting operations, such as insert and delete, can be realized by the combination of these 4 basic operations. The architecture is very regular and mainly composed of two basic cells, sort-cell and compare-cell. The latter is designed to generate control signals orchestrating the operation of sort cells which contain the sorted input sequences. Experimental results show that a single chip solution can achieve real-time performance based on 1.2 mu m CMOS double-metal technology.
URI: http://dx.doi.org/10.1007/BF02107058
http://hdl.handle.net/11536/1646
ISSN: 0922-5773
DOI: 10.1007/BF02107058
期刊: JOURNAL OF VLSI SIGNAL PROCESSING
Volume: 11
Issue: 3
起始頁: 273
結束頁: 280
顯示於類別:期刊論文