標題: TIMING-DRIVEN PARTIAL SCAN
作者: JOU, JY
CHENG, KT
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-十二月-1995
摘要: This partial scan approach reduces area overhead and performance degradation caused by test logic. Given an initial design that meets a target speed, the authors' algorithm selects a set of scan flip-flops that allows the circuit to meet performance requirements after the scan logic is added. if no such set exists, the algorithm selects a set that minimizes the total area increase caused by the scan logic and the subsequent performance optimization the circuit requires to meet target speed.
URI: http://dx.doi.org/10.1109/54.491238
http://hdl.handle.net/11536/1644
ISSN: 0740-7475
DOI: 10.1109/54.491238
期刊: IEEE DESIGN & TEST OF COMPUTERS
Volume: 12
Issue: 4
起始頁: 52
結束頁: 59
顯示於類別:期刊論文


文件中的檔案:

  1. A1995TF01400008.pdf