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dc.contributor.authorLIN, CYen_US
dc.contributor.authorJUAN, KCen_US
dc.contributor.authorCHANG, CYen_US
dc.contributor.authorPAN, FMen_US
dc.contributor.authorCHOU, PFen_US
dc.contributor.authorHUNG, SFen_US
dc.contributor.authorCHEN, LJen_US
dc.date.accessioned2014-12-08T15:03:03Z-
dc.date.available2014-12-08T15:03:03Z-
dc.date.issued1995-12-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/16.477764en_US
dc.identifier.urihttp://hdl.handle.net/11536/1634-
dc.description.abstractThis paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p(+)-gate devices, The characteristics and reliability for different gate structures (poly-Si, alpha-Si, poly-Si/poly-Si, poly-Si/alpha-Si, alpha-Si/poly-Si, and alpha-Si/alpha-Si) in p(+) polygate PMOS devices are investigated in detail, The suppression of boron penetration by the nitrided gate oxide is also discussed, The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p(+) polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate, Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance, The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p(+)-gate PMOS device for future dual-gate CMOS process, In addition, by employing a long time annealing at 600 degrees C prior to p(+)-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate, Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect.en_US
dc.language.isoen_USen_US
dc.titleA COMPREHENSIVE STUDY OF SUPPRESSION OF BORON PENETRATION BY AMORPHOUS-SI GATE IN P+-GATE PMOS DEVICESen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/16.477764en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume42en_US
dc.citation.issue12en_US
dc.citation.spage2080en_US
dc.citation.epage2088en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:A1995TH17200008-
dc.citation.woscount15-
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