標題: A COMPREHENSIVE STUDY OF SUPPRESSION OF BORON PENETRATION BY AMORPHOUS-SI GATE IN P+-GATE PMOS DEVICES
作者: LIN, CY
JUAN, KC
CHANG, CY
PAN, FM
CHOU, PF
HUNG, SF
CHEN, LJ
電控工程研究所
Institute of Electrical and Control Engineering
公開日期: 1-十二月-1995
摘要: This paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p(+)-gate devices, The characteristics and reliability for different gate structures (poly-Si, alpha-Si, poly-Si/poly-Si, poly-Si/alpha-Si, alpha-Si/poly-Si, and alpha-Si/alpha-Si) in p(+) polygate PMOS devices are investigated in detail, The suppression of boron penetration by the nitrided gate oxide is also discussed, The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p(+) polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate, Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance, The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p(+)-gate PMOS device for future dual-gate CMOS process, In addition, by employing a long time annealing at 600 degrees C prior to p(+)-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate, Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect.
URI: http://dx.doi.org/10.1109/16.477764
http://hdl.handle.net/11536/1634
ISSN: 0018-9383
DOI: 10.1109/16.477764
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 42
Issue: 12
起始頁: 2080
結束頁: 2088
顯示於類別:期刊論文


文件中的檔案:

  1. A1995TH17200008.pdf