|標題:||Performance Evaluation of Inter-Processor Communication for an Embedded Heterogeneous Multi-Core Processor|
Department of Computer Science
|關鍵字:||multi-core;inter-processor communication;performance evaluation;embedded system;heterogeneous multi-core processor|
|摘要:||Embedded systems often use a heterogeneous multi-core processor to improve performance and energy efficiency. This multi-core processor is composed of a general purpose processor (GPP), which manages the program flow and I/O, and a digital. signal processor (DSP), which processes mass data. An inter-processor communication (IPC) mechanism is thus required to exchange data between a GPP and a DSP. This paper uses comprehensive experiments to evaluate the IPC performance of an embedded heterogeneous multi-core processor under different design strategies. We further develop the IPC performance model and suggest dynamic adjustment of IPC strategies under environmental parameters and system resource constraints. Based on the results and findings, we improve the IPC performance of a voice over IP (VoIP) phone. Experimental results demonstrate that the GPP workload decreases significantly by 35% without sacrificing the functionalities and voice quality of the VolP system. Moreover, we apply the concept of dynamic adjustment of IPC strategies to an embedded media gateway. The simulation results demonstrate that the dynamic IPC strategy can considerably improve the system performance of the media gateway compared with the static IPC design approach.|
|期刊:||JOURNAL OF INFORMATION SCIENCE AND ENGINEERING|
|Appears in Collections:||Articles|
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.