標題: All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation
作者: Hsieh, Wei-Chih
Hwang, Wei
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Current efficiency;digital;linear regulator;push-pull;response time constraint;time interleaving
公開日期: 1-六月-2012
摘要: In this paper, an all digital push-pull linear voltage regulator is proposed that consists of a digital error detector, a voltage divider, a mode indicator, a pull device, and grouped push devices. The digital regulator is suitable for super-to near-threshold region operation by providing a variable output voltage that ranges from 0.5 to 1 V in steps of 0.1 V. The maximum load current is 100 mA for every output level. The current efficiency is 99.8% with only 164.5 mu A quiescent current on UMC 65-nm standard CMOS technology. A response time constraint is developed to provide a design guideline for (all) the digital control system. It describes the correlation between required speed of the digital control system, the output performance and the size of the decoupling capacitor. A time interleaving control technique is then proposed to have a tradeoff between output performance, quiescent current, and the size of decoupling capacitor.
URI: http://hdl.handle.net/11536/16286
ISSN: 1063-8210
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 20
Issue: 6
結束頁: 989
顯示於類別:期刊論文


文件中的檔案:

  1. 000304102000002.pdf