Title: A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
Authors: Tu, Ming-Hsien
Lin, Jihi-Yu
Tsai, Ming-Chien
Lu, Chien-Yu
Lin, Yuh-Jiun
Wang, Meng-Hsueh
Huang, Huan-Shun
Lee, Kuen-Di
Shih, Wei-Chiang (Willis)
Jou, Shyh-Jye
Chuang, Ching-Te
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: Low power;low voltage;negative bit-line (BL);subthreshold SRAM cell;timing tracing
Issue Date: 1-Jun-2012
Abstract: This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-inter-leaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with V-DD down to 0.35 V (similar to 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 mu W power. Data is held down to 0.275 V with 2.29 mu W Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V-DD around/above 1.0 V.
URI: http://hdl.handle.net/11536/16275
ISSN: 0018-9200
Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 47
Issue: 6
End Page: 1469
Appears in Collections:Articles


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