標題: A 2.37-Gb/s 284.8 mW Rate-Compatible (491,3,6) LDPC-CC Decoder
作者: Chen, Chih-Lung
Lin, Yu-Hsiang
Chang, Hsie-Chia
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Decoding scheduling;error correction;high throughput;low-density parity check convolutional code (LDPC-CC)
公開日期: 1-四月-2012
摘要: This paper presents a (491,3,6) time-varying low-density parity check convolutional code (LDPC-CC) decoder chip. This work combines the algorithm level, node level, and bit level optimizations to achieve over 2 Gb/s throughput with acceptable hardware cost and power. The algorithm level optimization is the on-demand variable node activation scheduling with concealing channel values, which can not only achieve twice faster decoding convergence speed than log-belief propagation (log-BP) algorithm, but also reduce the 17% message storage capacity. The node level optimization duplicates the check node units and variable node units and unfolds the message storage first-in-first-outs (FIFOs) so that the throughput becomes twelve multiplying with clock frequency. In the meantime, the bit level optimization is employed to retime the critical path such that the higher clock frequency can be achieved and message storage size is slightly reduced. Furthermore, a novel hybrid-partitioned FIFO is proposed to provide sufficient memory bandwidth to processing units and alleviate power consumption. With these schemes, a test chip of proposed LDPC-CC decoder has been fabricated in 90 nm CMOS technology with core area of 2.37 x 1.14 mm(2). Maximum throughput 2.37 Gb/s is measured under 1.2 V supply with energy efficiency of 0.024 nJ/bit/proc. Depending on the operation mode, power can be scaled down to 90.2 mW while maintaining 1.58 Gb/s at 0.8 V supply.
URI: http://hdl.handle.net/11536/16088
ISSN: 0018-9200
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 47
Issue: 4
結束頁: 817
顯示於類別:期刊論文


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  1. 000302494700004.pdf