標題: A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters
作者: Ho, Yingchieh
Su, Chauchin
電機工程學系
電控工程研究所
Department of Electrical and Computer Engineering
Institute of Electrical and Control Engineering
關鍵字: Bootstrapped circuit;energy efficient;inter-symbol interference (ISI);low-voltage;leakage current reduction low-power;sub-threshold circuit
公開日期: 1-五月-2012
摘要: This paper presents a 40-130 fJ/bit/ch on-chip data link design under a 0.1-0.3V power supply. A bootstrapped CMOS repeater is proposed to drive a 10 mm on-chip bus. It features a -V-DD to 2V(DD) swing to enhance the driving capability and reduces the sub-threshold leakage current. Additionally, a precharge enhancement scheme increases the speed of the data transmission, and a leakage current reduction technique suppresses ISI jitter. A test chip is fabricated in a 55 nm SPRVT Low-K CMOS process. The measured results demonstrate that for a 10 mm on-chip bus, the achievable data rate is 0.8-100 Mbps, and the energy consumption is 40-123 fJ per bit under 0.1-0.3 V-DD.
URI: http://hdl.handle.net/11536/15998
ISSN: 0018-9200
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 47
Issue: 5
結束頁: 1242
顯示於類別:期刊論文


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  1. 000303329600018.pdf