標題: Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique
作者: Ho, Yingchieh
Chang, Chiachi
Su, Chauchin
電機工程學系
電控工程研究所
Department of Electrical and Computer Engineering
Institute of Electrical and Control Engineering
關鍵字: Bootstrapped circuit;leakage-current reduction;low-voltage circuit;subthreshold circuit
公開日期: 1-一月-2012
摘要: This brief presents a bootstrapped CMOS inverter operated with a subthreshold power supply. In addition to improving the driving ability, a large gate voltage swing from - V-DD to 2V(DD) suppresses the subthreshold leakage current. As compared with other reported works, the proposed bootstrapped inverter uses fewer transistors operated in the subthreshold region. Therefore, our design has shorter delay time. The Monte Carlo analysis results indicate that a sigma of delay time is only 6.3 ns under the process and temperature variations with 200-mV operation. Additionally, a test chip is fabricated in the 90-nm SPRVT low-K CMOS process. Chip measurement results demonstrate the feasibility of operating ten-stage bootstrapped inverters with a 200-fF loading of each stage at 200-mV V-DD. The test chip is able to achieve 10-MHz clock rate at 200 mV V-DD, the power consumption is 1.01 mu W, and the leakage power is 107 nW.
URI: http://dx.doi.org/10.1109/TCSII.2011.2174674
http://hdl.handle.net/11536/15854
ISSN: 1549-7747
DOI: 10.1109/TCSII.2011.2174674
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 59
Issue: 1
起始頁: 55
結束頁: 59
顯示於類別:期刊論文


文件中的檔案:

  1. 000302098200012.pdf