標題: A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine
作者: Liu, Po-Chun
Chang, Hsie-Chia
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Advanced Encryption Standard (AES);cryptography;differential power analysis (DPA);ring oscillators;true random number generator
公開日期: 1-二月-2012
摘要: The differential power analysis (DPA) has become a big threat to crypto chips since it can efficiently disclose the secret key without much effort. Several methods have been proposed in literatures to resist the DPA attack, but they largely increase the hardware cost and severely degrade the throughput. In this brief, a security problem based on ring oscillators is resolved by a new architecture with self-generated true random sequence. The true random-based architecture is implemented with an Advanced Encryption Standard (AES) crypto engine using UMC 90-nm CMOS technology. The DPA-resistant AES engine can achieve 2.97-Gb/s throughput at an operating frequency of 255 MHz with a 0.104-mm(2) cell area. The proposed DPA countermeasure circuit has only 6.2% area and 18.5% power overhead without throughput degradation.
URI: http://dx.doi.org/10.1109/TCSII.2011.2180094
http://hdl.handle.net/11536/15842
ISSN: 1549-7747
DOI: 10.1109/TCSII.2011.2180094
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 59
Issue: 2
起始頁: 103
結束頁: 107
顯示於類別:期刊論文


文件中的檔案:

  1. 000302101000007.pdf