標題: New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
作者: Yeh, Chih-Ting
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Electrostatic discharge (ESD);holding voltage;mixed-voltage I/O buffers;power-rail ESD clamp circuit
公開日期: 1-三月-2012
摘要: A new 2 x VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide 1-V (1 x VDD) devices and a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. This new design has a low standby leakage current by reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit. The proposed design with an SCR width of 50 mu m can achieve a 6.5-kV human-body-model ESD level, a 300-V machine-model ESD level, and a low standby leakage current of only 103.7 nA at room temperature under the normal circuit operating condition with 1.8 V bias.
URI: http://dx.doi.org/10.1109/TCSII.2012.2184372
http://hdl.handle.net/11536/15809
ISSN: 1549-7747
DOI: 10.1109/TCSII.2012.2184372
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 59
Issue: 3
起始頁: 178
結束頁: 182
顯示於類別:期刊論文


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