標題: Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
作者: Huang, Juinn-Dar
Chen, Chia-I
Hsu, Wan-Ling
Lin, Yen-Ting
Jou, Jing-Yang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Behavioral synthesis;distributed register-file;performance optimization;low-power;resource binding;scheduling
公開日期: 1-二月-2012
摘要: In deep-submicron era, wire delay is becoming a bottleneck while pursuing higher system clock speed. Several distributed register (DR) architectures are proposed to cope with this problem by keeping most wires local. In this article, we propose the distributed register-file microarchitecture with inter-island delay (DRFM-IID). Though DRFM-IID is also one of the DR-based architectures, it is considered more practical than the previously proposed DRFM, in terms of delay model. With such delay consideration, the synthesis task is inherently more complicated than the one without inter-island delay concern since uncertain interconnect latency is very likely to seriously impact on the whole system performance. Therefore we also develop a performance-driven architectural synthesis framework targeting DRFM-IID. Several factors for evaluating the quality of results, such as number of inter-island transfers, timing-criticality of transfer, and resource utilization balancing, are adopted as the guidance while performing architectural synthesis for better optimization outcomes. The experimental results show that the latency and the number of inter-cluster transfers can be reduced by 26.9% and 37.5% on average; and the latter is commonly regarded as an indicator for power consumption of on-chip communication.
URI: http://dx.doi.org/10.1587/transfun.E95.A.559
http://hdl.handle.net/11536/15659
ISSN: 0916-8508
DOI: 10.1587/transfun.E95.A.559
期刊: IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
Volume: E95A
Issue: 2
起始頁: 559
結束頁: 566
顯示於類別:期刊論文


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  1. 000300472000016.pdf