標題: Oxide Thinning and Structure Scaling Down Effect of Low-Temperature Poly-Si Thin-Film Transistors
作者: Ma, William Cheng-Yu
Chiang, Tsung-Yu
Lin, Je-Wei
Chao, Tien-Sheng
電子物理學系
Department of Electrophysics
關鍵字: Gate oxide thickness;low-temperature poly-Si thin-film transistors (LTPS-TFTs);scaling down
公開日期: 1-一月-2012
摘要: In this paper, the gate oxide thickness, and the channel length and width of low-temperature poly-Si thin-film transistors (LTPS-TFTs) have been comprehensively studied. The scaling down of gate oxide thickness from 50 to 20 nm significantly improves the subthreshold swing (S. S.) of LTPS-TFTs from 1.797 V/decade to 0.780 V/ decade and the threshold voltage V(TH) from 10.87 V to 5.00 V. Moreover, the threshold voltage V(TH) roll-off is also improved with the scaling down of gate oxide thickness due to gate capacitance density enhancement. The channel length scaling down also shows significant subthreshold swing S. S. improvement due to a decreasing of the channel grain boundary trap density. However, the scaling down of channel length also increases the series resistance effect, resulting in the degradation of the field-effect mobility mu(FE). Therefore, the channel length dependence of field-effect mobility mu(FE) is slightly different with different channel width due to the competition of channel grain boundary trap density effect and series resistance effect.
URI: http://dx.doi.org/10.1109/JDT.2011.2162938
http://hdl.handle.net/11536/15303
ISSN: 1551-319X
DOI: 10.1109/JDT.2011.2162938
期刊: JOURNAL OF DISPLAY TECHNOLOGY
Volume: 8
Issue: 1
起始頁: 12
結束頁: 17
顯示於類別:期刊論文


文件中的檔案:

  1. 000298888800002.pdf