標題: A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder
作者: Liao, Yuan-Hsin
Li, Gwo-Long
Chang, Tian-Sheuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Binary arithmetic coding;CABAC;entropy decoding;H.264/AVC;syntax parsing
公開日期: 1-二月-2012
摘要: In this paper, a high throughput context-based adaptive binary arithmetic coding decoder design is proposed. This decoder employs a syntax element prediction method to solve pipeline hazard problems. It also uses a new hybrid memory two-symbol parallel decoding in order to enhance performance as well as to reduce costs. The critical path delay of the two-symbol binary arithmetic decoding engine is improved by 28% with an efficient mathematical transform. Experimental results show that the throughput of our proposed design can reach 485.76 Mbins/s in the high bit-rate coding and 446.2 Mbins/s on average at 264MHz operating frequency, which is sufficient to support H.264/AVC level 5.1 real-time decoding.
URI: http://dx.doi.org/10.1109/TCSVT.2011.2160752
http://hdl.handle.net/11536/15222
ISSN: 1051-8215
DOI: 10.1109/TCSVT.2011.2160752
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
Volume: 22
Issue: 2
起始頁: 272
結束頁: 281
顯示於類別:期刊論文


文件中的檔案:

  1. 000300105900010.pdf