標題: A ISS-Length Full Code Rate 333Mbps 1.08mm(2) Radix-4 Hybrid-Trellis Thrbo Decoder with Zero Patching for 3GPP LTE-A
作者: Chang, Po-Hsun
Lin, Chen-Yang
Sun, Chia-Hsiang
Liao, Yen-Chin
Chang, Hsie-Chia
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Jan-2018
摘要: Decoding high code rate Thrbo codes by their reciprocal dual trellis has been shown to be potentially beneficial in implementation due to the simpler trellis structures. However, reciprocal dual trellis decoders' complexity grows significantly when the code rate is less than 1/2. Further, designing a multi-code rate reciprocal dual trellis decoder is even more challenging if periodical puncturing patterns is not always available. In this paper, a radix-4 hybrid-trellis LTE-A turbo decoder with a controller switching between the conventional trellis and the reciprocal dual trellis is presented. To accommodate all the rates defined in LTE-A, a zero patching scheme is proposed to create the periodical puncturing patterns required by the reciprocal dual trellis decoding. The implementation of the proposed decoder supports all the code rates, from 1/3 to 0.95, and all the 188 block lengths. Fabricated in TSMC TN28HPM process, the post-layout simulations show the proposed decoder could achieve 333Mbps at 6 iterations under 263MHz operating frequency. The core area is 1.08 mm(2), and the decoder draws 295.57 mW of power with energy efficiency of 0.148(nJ/bitJiter).
URI: http://hdl.handle.net/11536/150857
ISSN: 0271-4302
期刊: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
Appears in Collections:Conferences Paper