標題: Timing Macro Modeling for Efficient Hierarchical Timing Analysis
作者: Jiang, Iris Hui-Ru
Lee, Pei-Yu
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Static timing analysis;hierarchical timing analysis;timing macro modeling;interface logic model;extracted timing model
公開日期: 1-Jan-2018
摘要: As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this paper, we discuss timing macro modeling, which is the key to enable efficient and accurate hierarchical timing analysis. We briefly review conventional models and recent research progresses in timing macro modeling. We try to answer the following questions: How can timing macro models be made compact and accurate? How do state-of-the art works maintain model accuracy, model size, model generation performance, and model usage performance? Finally, future research directions on timing macro modeling are identified.
URI: http://dx.doi.org/10.1109/ISVLSI.2018.00134
http://hdl.handle.net/11536/150728
ISSN: 2159-3469
DOI: 10.1109/ISVLSI.2018.00134
期刊: 2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI)
起始頁: 714
結束頁: 714
Appears in Collections:Conferences Paper