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dc.contributor.authorWu, Yu-Zeen_US
dc.contributor.authorChao, Mango C. -T.en_US
dc.date.accessioned2019-04-02T05:59:43Z-
dc.date.available2019-04-02T05:59:43Z-
dc.date.issued2010-11-01en_US
dc.identifier.issn1084-4309en_US
dc.identifier.urihttp://dx.doi.org/10.1145/1870109.1870119en_US
dc.identifier.urihttp://hdl.handle.net/11536/150188-
dc.description.abstractThis article presents several scan-cell reordering techniques to reduce the signal transitions during the test mode while preserving the don't-care bits in the test patterns for a later optimization. Combined with a pattern-filling technique, the proposed scan-cell reordering techniques can utilize both high response correlations and pattern correlations to simultaneously minimize scan-out and scan-in transitions. Those scan-shift transitions can be further reduced by selectively using the inverse connections between scan cells. In addition, the trade-off between routing overhead and power consumption can also be controlled by the proposed scan-cell reordering techniques. A series of experiments are conducted to demonstrate the effectiveness of each of the proposed techniques individually.en_US
dc.language.isoen_USen_US
dc.subjectAlgorithmsen_US
dc.subjectDesignen_US
dc.subjectScan testingen_US
dc.subjectDFTen_US
dc.subjectlow-power testingen_US
dc.titleScan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubesen_US
dc.typeArticleen_US
dc.identifier.doi10.1145/1870109.1870119en_US
dc.identifier.journalACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMSen_US
dc.citation.volume16en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000284931600010en_US
dc.citation.woscount1en_US
Appears in Collections:Articles