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dc.contributor.authorLin, Yi-Minen_US
dc.contributor.authorChen, Chih-Lungen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:21:06Z-
dc.date.available2014-12-08T15:21:06Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-4434-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/15002-
dc.identifier.urihttp://dx.doi.org/10.1109/ASSCC.2009.5357174en_US
dc.description.abstractThis paper provides a soft BCH decoder using error magnitudes to deal with least reliable bits. With soft information from the previous decoder defined in digital video broadcasting (DVB), the proposed soft BCH decoder provides much lower complexity and latency than the traditional hard BCH decoder while still maintaining performance. The proposed error locator evaluator architecture evaluates error locations without Chien search, leading to high throughput. Borck-Pereyra error magnitudes solvers (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The experimental result reveals that our proposed soft (32400, 32208) BCH decoder defined in DVB-S2 system can save 50.0% gate-count and achieve 314.5Mbps in standard CMOS 90nm technology.en_US
dc.language.isoen_USen_US
dc.subjectError correction codingen_US
dc.subjectBose-Chaudhuri-Hochquenghem (BCH) codesen_US
dc.subjectDigital Video Broadcastingen_US
dc.titleA 26.9K 314.5Mbps Soft (32400,32208) BCH Decoder Chip for DVB-S2 Systemen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ASSCC.2009.5357174en_US
dc.identifier.journal2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)en_US
dc.citation.spage373en_US
dc.citation.epage376en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000298194200094-
Appears in Collections:Conferences Paper


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