Title: A 26.9K 314.5Mbps Soft (32400,32208) BCH Decoder Chip for DVB-S2 System
Authors: Lin, Yi-Min
Chen, Chih-Lung
Chang, Hsie-Chia
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: Error correction coding;Bose-Chaudhuri-Hochquenghem (BCH) codes;Digital Video Broadcasting
Issue Date: 2009
Abstract: This paper provides a soft BCH decoder using error magnitudes to deal with least reliable bits. With soft information from the previous decoder defined in digital video broadcasting (DVB), the proposed soft BCH decoder provides much lower complexity and latency than the traditional hard BCH decoder while still maintaining performance. The proposed error locator evaluator architecture evaluates error locations without Chien search, leading to high throughput. Borck-Pereyra error magnitudes solvers (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The experimental result reveals that our proposed soft (32400, 32208) BCH decoder defined in DVB-S2 system can save 50.0% gate-count and achieve 314.5Mbps in standard CMOS 90nm technology.
URI: http://hdl.handle.net/11536/15002
http://dx.doi.org/10.1109/ASSCC.2009.5357174
ISBN: 978-1-4244-4434-2
DOI: 10.1109/ASSCC.2009.5357174
Journal: 2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)
Begin Page: 373
End Page: 376
Appears in Collections:Conferences Paper


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