標題: A Micro-Network on Chip with 10-Gb/s Transmission Link
作者: Liu, Wei-Chang
Lin, Chih-Hsien
Jou, Shyh-Jye
Lu, Hung-Wen
Su, Chau-Chin
Hong, Kai-Wei
Cheng, Kuo-Hsing
Yang, Shyue-Wen
Sheu, Ming-Hwa
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2009
摘要: In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13 mu m CMOS technology. The core area of this chip is 990 mu m*1600 mu m and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.
URI: http://hdl.handle.net/11536/14999
http://dx.doi.org/10.1109/ASSCC.2009.5357256
ISBN: 978-1-4244-4434-2
DOI: 10.1109/ASSCC.2009.5357256
期刊: 2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)
起始頁: 277
結束頁: 280
Appears in Collections:Conferences Paper


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