標題: A Generic Multi-Dimensional Scan-Control Scheme for Test-Cost Reduction
作者: Lin, Chia-Yi
Chen, Hung-Ming
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: DFT;low power;scan chain;compression;test data volume
公開日期: 1-十一月-2011
摘要: This paper proposes a generic multi-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping (selectively load/unload) many long scan chain switching activities. Based on the two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. We can further extend the scheme to a generic N dimension test scheme. The proposed scheme skips many unnecessary don't care (X) patterns to reduce the test data volume and test time. The experimental results of the proposed 2-D scheme achieve significant improvement in shift power reduction, test volume and test time reduction. Compared with traditional single scan chain design, the large benchmark b17 of ITC'99 has over 50% reduction in test data volume and over 40% reduction in test time with little area overhead, around 1% routing overhead, and the power reduction is over 97%.
URI: http://hdl.handle.net/11536/14943
ISSN: 1016-2364
期刊: JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Volume: 27
Issue: 6
起始頁: 1943
結束頁: 1957
顯示於類別:期刊論文


文件中的檔案:

  1. 000297605900010.pdf