|標題:||A Generic Multi-Dimensional Scan-Control Scheme for Test-Cost Reduction|
Department of Electronics Engineering and Institute of Electronics
|關鍵字:||DFT;low power;scan chain;compression;test data volume|
|摘要:||This paper proposes a generic multi-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping (selectively load/unload) many long scan chain switching activities. Based on the two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. We can further extend the scheme to a generic N dimension test scheme. The proposed scheme skips many unnecessary don't care (X) patterns to reduce the test data volume and test time. The experimental results of the proposed 2-D scheme achieve significant improvement in shift power reduction, test volume and test time reduction. Compared with traditional single scan chain design, the large benchmark b17 of ITC'99 has over 50% reduction in test data volume and over 40% reduction in test time with little area overhead, around 1% routing overhead, and the power reduction is over 97%.|
|期刊:||JOURNAL OF INFORMATION SCIENCE AND ENGINEERING|
|Appears in Collections:||Articles|
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