標題: Effects of Channel Width and Nitride Passivation Layer on Electrical Characteristics of Polysilicon Thin-Film Transistors
作者: Liao, Chia-Chun
Lin, Min-Chen
Chiang, Tsung-Yu
Chao, Tien-Sheng
電子物理學系
Department of Electrophysics
關鍵字: Gate-induced drain leakage (GIDL);grain boundary;intragrain;kink effect;radical
公開日期: 1-十一月-2011
摘要: SiN passivation layers were found to yield better performance, suppress the kink effect, and improve the gate leakage current and gate-induced drain leakage (GIDL) of polysilicon thin-film transistors (TFTs). The SiN passivation layers deposited under different deposition conditions possess different characteristics due to their varying passivation effect. A physical mechanism is proposed to explain the double-hump phenomenon induced by incomplete trap passivation. Based on the analysis of width dependence, the better performance of the samples with SiN passivation layers was attributed not only to radical passivation of the defect states but also to radical passivation of preexisting defects in the gate oxide. Furthermore, using SiN passivation layers improves immunity to positive gate bias stress, negative gate bias stress, and hot-carrier stressing. Moreover, the manufacturing processes are simple (without the long processing time plasma treatment requires) and compatible with TFT processes.
URI: http://dx.doi.org/10.1109/TED.2011.2165214
http://hdl.handle.net/11536/14693
ISSN: 0018-9383
DOI: 10.1109/TED.2011.2165214
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 58
Issue: 11
起始頁: 3812
結束頁: 3819
顯示於類別:期刊論文


文件中的檔案:

  1. 000296099400021.pdf