|標題:||Methodology of Generating Dual-Cell-Aware Tests|
Chao, Mango C. -T.
Department of Electronics Engineering and Institute of Electronics
|摘要:||This paper introduces a novel fault model, called the dual-cell-aware (DCA) fault model, which targets the short defects locating between two adjacent standard cells placed in the layout. A layout-based methodology is also presented to automatically extract valid DCA faults from targeted designs and cell libraries. The identified DCA faults are outputted in a format that can be applied to a commercial ATPG tool for test generation. The result of ATPG and fault simulation based on industrial designs have demonstrated that the DCA faults cannot be fully covered by the tests of conventional fault models including stuck-at, transition, bridge and cell-aware faults and hence require their own designated tests to detect.|
|期刊:||2017 IEEE 35TH VLSI TEST SYMPOSIUM (VTS)|
|Appears in Collections:||Conferences Paper|