Title: 3D Ferroelectric-like NVM/CMOS Hybrid Chip by sub-400 degrees C Sequential Layered Integration
Authors: Lien, Yu-Chung
Shieh, Jia-Min
Huang, Wen-Hsien
Hsieh, Wei-Shang
Tu, Cheng-Hui
Wang, Chieh
Shen, Chang-Hong
Chou, Tung-Huan
Chen, Min-Cheng
Huang, Jung Y.
Pan, Ci-Ling
Lai, Yin-Chieh
Hu, Chenming
Yang, Fu-Liang
Department of Photonics
Issue Date: 1-Jan-2012
Abstract: For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm(2)/V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400 degrees C new-type metal-ion (Eu+3)-mediated atomic-polar-structured (Eu+3-APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed dat-storage application era.
URI: http://hdl.handle.net/11536/146347
Appears in Collections:Conferences Paper