標題: Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors
作者: Lai, Wei-Ting
Yang, Kuo-Ching
Liao, Po-Hsiang
George, Tom
Li, Pei-Wen
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: gate-stack;SiGe;self-organized;Ge dot;interface;size-tunable;MOSIN
公開日期: 11-Feb-2016
摘要: We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe-nanopatterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5-90 nm), the SiO2 thickness (3-4 nm), and the SiGe-shell thickness (2-15 nm) have been demonstrated, enabling a practically achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive X-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5 x 10(11) cm(-2) eV(-1) and fixed charge densities of 1-5 x 10(11) cm(-2), suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1-xGex shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.
URI: http://dx.doi.org/10.3389/fmats.2016.00005
http://hdl.handle.net/11536/146005
ISSN: 2296-8016
DOI: 10.3389/fmats.2016.00005
期刊: FRONTIERS IN MATERIALS
Volume: 3
起始頁: 0
結束頁: 0
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