Title: A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
Authors: Wu, Shang-Lin
Li, Kuang-Yu
Huang, Po-Tsang
Hwang, Wei
Tu, Ming-Hsien
Lung, Sheng-Chi
Peng, Wei-Sheng
Huang, Huan-Shun
Lee, Kuen-Di
Kao, Yung-Shin
Chuang, Ching-Te
Department of Electronics Engineering and Institute of Electronics
Keywords: Low voltage;low power;static random access memory (SRAM);write-assist;power-gating;near-threshold
Issue Date: 1-Jul-2017
Abstract: This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power gating to facilitate lower NAP (Sleep) mode voltage/power and faster wake-up for the cell array, and low-swing global read bit-line (GRBL) with integrated low-swing voltage precharger to improve read performance and reduce the dynamic read power. A cell Vtrip-tracking write-assist (VTWA) lowers the selected sub-array supply to cell inverter trip voltage to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected sub-array. The 256-kb test chip is implemented in UMC 28-nm high-kappa metal-gate (H kappa MG) CMOS technology with macro area of 1058.22 x 374.76 mu m(2). Error-free full functionality is achieved from 0.9 down to 0.5 V (limited by read VMIN) without redundancy. The low-swing GRBL reduces dynamic power by 6.5% (8.0%) at 0.9 V (0.6 V). The VTWA improves the write VMIN by 75 mV (from 0.525 to 0.45 V). The measured maximum operation frequency is 735 MHz (20 MHz) at 0.9 V (0.5 V), TT corner, 25(omicron).
URI: http://dx.doi.org/10.1109/TCSI.2017.2681738
ISSN: 1549-8328
DOI: 10.1109/TCSI.2017.2681738
Volume: 64
Begin Page: 1791
End Page: 1802
Appears in Collections:Articles