標題: A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage
作者: Nidhi, Karuna
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: CMOS process;ESD implantation;junction field-effect transistor (JFET);pinch-off voltage (V-p);SPICE;zero-bias drain current (I-DS0)
公開日期: 1-Jul-2017
摘要: A novel horizontal n-channel junction field-effect transistor (n-JFET) device is proposed and verified in a 0.25-mu m bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to improve ESD robustness of the I/O devices. Device parameters such as the pinch-off voltage (V-P) and the zero-bias drain current (I-DS0) of the proposed n-JFET device can be modified by adjusting the P+ separation (L) in the layout. With the adjustable pinch-off voltages, this device can be used for different circuit applications. The 2-D device simulations with technology computer aided design are used to analyze the depletion region and to verify the pinch-off voltage under different L values. The pinch-off voltage remains almost unchanged with the temperature variations. In addition, SPICE simulation results show good agreement with the experimental silicon (Si) data in term of I-D-V-D and I-D-V-G.
URI: http://dx.doi.org/10.1109/TED.2017.2706423
http://hdl.handle.net/11536/145635
ISSN: 0018-9383
DOI: 10.1109/TED.2017.2706423
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 64
起始頁: 2812
結束頁: 2819
Appears in Collections:Articles