Title: A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing
Authors: Chang, Meng-Fan
Lin, Chien-Chen
Lee, Albert
Chiang, Yen-Ning
Kuo, Chia-Chen
Yang, Geng-Hau
Tsai, Hsiang-Jen
Chen, Tien-Fu
Sheu, Shyh-Shyuan
National Chiao Tung University
Department of Computer Science
Keywords: Nonvolatile memory (NVM);nonvolatile ternary content-addressable-memory (nvTCAM);resistive RAM (ReRAM);TCAM
Issue Date: 1-Jun-2017
Abstract: Existing nonvolatile ternary content-addressable-memory (nvTCAM) suffers from limited word-length (WDL), large write-energy (E-W) and search-energy (E-S), and large cell area (A). This paper develops a 3T1R nvTCAM cell using a single multiple-level cell (MLC)-resistive RAM (ReRAM) device to achieve long WDL, lower E-W and E-S, and reduced cell area. Two peripheral control schemes were developed, dual-replica-row self-timed and invalid-entry power consumption suppression (IEPCS), for the suppression of dc current in 3T1R nvTCAM cells in order to reduce E-S. Two versions of the IEPCS scheme were developed (basic and charge-recycle-controlled) to alter the tradeoff between area overhead and power consumption in the updating of invalid-bits. A 128 b x 64 b 3T1R nvTCAM macro was fabricated using back-end-of-line ReRAM under 90-nm CMOS process. The fabricated MLC-based 3T1R nvTCAM macro achieved sub-1-ns search-delay and sub-6-ns wake-up time with supply voltage of 1 V and WDL = 64 b.
URI: http://dx.doi.org/10.1109/JSSC.2017.2681458
ISSN: 0018-9200
DOI: 10.1109/JSSC.2017.2681458
Volume: 52
Begin Page: 1664
End Page: 1679
Appears in Collections:Articles