標題: High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
作者: Wu, Tsung-Ta
Huang, Wen-Hsien
Yang, Chih-Chao
Chen, Hung-Chun
Hsieh, Tung-Ying
Lin, Wei-Sheng
Kao, Ming-Hsuan
Chen, Chiu-Hao
Yao, Jie-Yi
Jian, Yi-Ling
Hsu, Chiung-Chih
Lin, Kun-Lin
Shen, Chang-Hong
Chueh, Yu-Lun
Shieh, Jia-Min
光電工程學系
光電工程研究所
Department of Photonics
Institute of EO Enginerring
公開日期: 2-May-2017
摘要: Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (I-on)/subthreshold swing (S.S.) of 181 mu A/mu m/107 mV/dec and 188 mu A/mu m/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at V-DD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.
URI: http://dx.doi.org/10.1038/s41598-017-01012-y
http://hdl.handle.net/11536/145447
ISSN: 2045-2322
DOI: 10.1038/s41598-017-01012-y
期刊: SCIENTIFIC REPORTS
Volume: 7
起始頁: 0
結束頁: 0
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